Memory - Revision history

Michael: /* Kernel Segments */ More emphasis on mapping and caching properties

2009-07-29T04:23:29Z

Kernel Segments: More emphasis on mapping and caching properties

Michael: /* Kernel Segment 2 */ Defined KSEG2 and how Xinu (doesn't) use it

2009-07-29T01:39:04Z

Kernel Segment 2: Defined KSEG2 and how Xinu (doesn't) use it

Michael: /* User Segment */ User segment uses fast exception handler

2009-07-29T01:33:09Z

User Segment: User segment uses fast exception handler

Michael: /* KSEG1 under Xinu */ re wiki-linked flash memory

2009-07-29T01:28:59Z

KSEG1 under Xinu: re wiki-linked flash memory

Michael: /* Flash Memory */ Moved to Flash Memory

2009-07-29T01:28:39Z

Flash Memory: Moved to Flash Memory

Michael: /* Kernel Segment 1 */ Defined KSEG1 and how Xinu uses it

2009-07-29T01:28:01Z

Kernel Segment 1: Defined KSEG1 and how Xinu uses it

Michael: /* User Segment under Xinu */ wiki-link memory management

2009-07-29T01:12:18Z

User Segment under Xinu: wiki-link memory management

Michael: /* KSEG0 under Xinu */ Header level correction

2009-07-29T01:06:05Z

KSEG0 under Xinu: Header level correction

Michael: /* Kernel Segment 0 */ Defined KSEG0 and how Xinu uses it

2009-07-29T01:05:41Z

Kernel Segment 0: Defined KSEG0 and how Xinu uses it

Michael: Boldfaced mapped/cached at top of page

2009-07-29T00:39:02Z

Boldfaced mapped/cached at top of page

@@ Line 34: / Line 34: @@
 === Kernel Segment 0 ===
-The first kernel segment, or KSEG0, is the range of memory addresses from <tt>0x8000 0000</tt> through <tt>0x9FFF FFFF</tt>.  This memory unmapped and cached, meaning that when the processor attempts to access an address in this range it will not consult the memory manager for a mapping, but will store and modifications in the on-chip memory cache.  '''Note''' that when allocating memory for a device driver that will be using DMA, the caching effects could lead to major headaches.  If memory is being given to a hardware backend it should be mapped into the range of [[#Kernel Segment 1|KSEG1]].
+The first kernel segment, or KSEG0, is the range of memory addresses from <tt>0x8000 0000</tt> through <tt>0x9FFF FFFF</tt>.  This memory '''unmapped''' and '''cached''', meaning that when the processor attempts to access an address in this range it will not consult the memory manager for a mapping, but will store and modifications in the on-chip memory cache.  '''Note''' that when allocating memory for a device driver that will be using DMA, the caching effects could lead to major headaches.  If memory is being given to a hardware backend it should be mapped into the range of [[#Kernel Segment 1|KSEG1]].
 On many MIPS processors the first page (4096 bytes) of KSEG0 is considered to be reserved system space where small amounts of specialized code can be loaded for fast execution.  Typically, this memory is used for exception handling and the following sections are reserved for the following:
@@ Line 56: / Line 56: @@
 === Kernel Segment 1 ===
-The second kernel segment, or KSEG1, is the range of memory addresses from 0xA000 0000 through 0xBFFF FFFF. This memory unmapped and uncached, meaning that when the processor attempts to access an address in this range it will not consult the memory manager for a mapping and it ''will'' bypass the on-chip memory cache for memory loads and stores.
+The second kernel segment, or KSEG1, is the range of memory addresses from 0xA000 0000 through 0xBFFF FFFF. This memory '''unmapped''' and '''uncached''', meaning that when the processor attempts to access an address in this range it will not consult the memory manager for a mapping and it ''will'' bypass the on-chip memory cache for memory loads and stores.
 By skipping the hardware cache, KSEG1 will see slower memory accesses because it must get data directly from the RAM.  Because of this, it is not typical to use KSEG1 for normal kernel operations, rather this segment is useful for accessing memory that is mapped to some other hardware device on the platform.  These mappings will either be pre-existing, so they are out-of-range of physical memory addresses, or they will be dynamically allocated memory that will be shared between the operating system and some hardware device.
@@ Line 75: / Line 75: @@
 === Kernel Segment 2 ===
-The third kernel segment, or KSEG2, is the range of memory addresses from 0xC000 0000 through 0xFFFF FFFF. This memory is both mapped and cached, meaning that the processor will consult the memory manager for a mapping and store memory modifications in the on-chip cache.
+The third kernel segment, or KSEG2, is the range of memory addresses from 0xC000 0000 through 0xFFFF FFFF. This memory is both '''mapped''' and '''cached''', meaning that the processor will consult the memory manager for a mapping and store memory modifications in the on-chip cache.
 Like the user segment of memory any attempt to access memory in KSEG2 will result in the processor querying the memory manager and the TLB to find a mapping.  If a mapping does not exist the processor will generate a TLB load or store exception and the operating system must fill the TLB entry.  Unlike USEG, a TLB exception will not jump to the "fast" handler and instead follow the normal path for exception handling through the generic exception mechanism.

@@ Line 74: / Line 74: @@
 === Kernel Segment 2 ===
-The last segment of MIPS memory is located at <tt>0xC000 0000</tt> and ends at <tt>0xFFFF FFFF</tt>, giving the kernel one gigabyte of fully mapped memory.  Similar to the user segment, the Embedded XINU team has not looked extensively into the usefulness of this segment.
 == References ==
 Sweetman, Dominic. ''See MIPS Run''. San Francisco: Morgan Kaufmann Publishers, 2007.

← Older revision		Revision as of 01:33, 29 July 2009
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	Under normal operation, when an address in this memory range is accessed, the processor will query the memory management unit is consulted for a mapping. In turn this will ask the translation lookaside buffer (TLB), and if no mapping is found cause a TLB load or store exception. When this exception occurs, the operating system is consulted and should write the correct mapping to the TLB and return from the exception handler.		Under normal operation, when an address in this memory range is accessed, the processor will query the memory management unit is consulted for a mapping. In turn this will ask the translation lookaside buffer (TLB), and if no mapping is found cause a TLB load or store exception. When this exception occurs, the operating system is consulted and should write the correct mapping to the TLB and return from the exception handler.
		+
		+	It should be noted that when a TLB exception occurs in the USEG range of addresses, a special "fast" exception handler is consulted instead of the normal exception handler. This fast handler is at most 32 instructions long and begins at <tt>0x8000 0000</tt>.

	=== User Segment under Xinu ===		=== User Segment under Xinu ===

@@ Line 67: / Line 67: @@
 * Broadcom Wireless LAN controller registers at <tt>0xB800 5000</tt>,
 * Broadcom 47xx RoboSwitch registers at <tt>0xB800 6000</tt>, and
-* [[Flash]] memory (4 MB) read mapped beginning at <tt>0xBC00 0000</tt>.
+* [[Flash memory]] (4 MB) read mapped beginning at <tt>0xBC00 0000</tt>.
 Certain drivers (such as the [[Ethernet]] driver), also take advantage of shared memory between the operating system and the hardware.  This requires the use of dynamically allocated kernel memory (originating in KSEG0), that has been mapped to KSEG1 address range.  This is not problematic because both KSEG0 and KSEG1 use a 1-1 memory mapping.  With the Ethernet driver of Embedded Xinu, the shared memory that is in KSEG1 hold the DMA descriptor rings and the Ethernet packet buffers to store the packets in.

@@ Line 73: / Line 73: @@
 === Kernel Segment 2 ===
 The last segment of MIPS memory is located at <tt>0xC000 0000</tt> and ends at <tt>0xFFFF FFFF</tt>, giving the kernel one gigabyte of fully mapped memory.  Similar to the user segment, the Embedded XINU team has not looked extensively into the usefulness of this segment.
 == References ==
 Sweetman, Dominic. ''See MIPS Run''. San Francisco: Morgan Kaufmann Publishers, 2007.

@@ Line 53: / Line 53: @@
 === Kernel Segment 1 ===
-These devices appear to begin at <tt>0xB800 0000</tt> with the Broadcom I/O controller on IRQ 3 which holds the [[GPIO]] registers from <tt>0xB800 0060</tt> to <tt>0xB800 006F</tt> and the two [[UART]] ports from <tt>0xB800 0300</tt> to <tt><0xB800 0307/tt> and from <tt>0xB800 0400</tt> to <tt>0xB800 0407</tt>.
+The second kernel segment, or KSEG1, is the range of memory addresses from 0xA000 0000 through 0xBFFF FFFF. This memory unmapped and uncached, meaning that when the processor attempts to access an address in this range it will not consult the memory manager for a mapping and it ''will'' bypass the on-chip memory cache for memory loads and stores.
-From there, devices are seperated by 0x1000 bytes beginning with the Broadcom Ethernet 47xx (possibly 4401) device at <tt>0xB800 1000</tt> on IRQ 4.  The MIPS 32 CPU on IRQ 5 is located at <tt>0xB800 2000</tt>, a Broadcom USB controller on IRQ 6 is located at <tt>0xB800 3000</tt>, a DD SDRAM Controller on IRQ 3 is found at <tt>0xB800 4000</tt>, the Broadcom Wireless LAN controller on IRQ 2 is at <tt>0xB800 5000</tt>, and finally the Broadcom 47xx Robo Switch core on IRQ 3 responds to addresses beginning with <tt>0xB800 6000</tt>.
+By skipping the hardware cache, KSEG1 will see slower memory accesses because it must get data directly from the RAM.  Because of this, it is not typical to use KSEG1 for normal kernel operations, rather this segment is useful for accessing memory that is mapped to some other hardware device on the platform.  These mappings will either be pre-existing, so they are out-of-range of physical memory addresses, or they will be dynamically allocated memory that will be shared between the operating system and some hardware device.
-After these devices is [[Flash driver|Flash]] memory which begins at <tt>0xBC00 0000</tt> and is 4 megabytes in size (lasting until <tt>0xBC3F FFFF</tt>).
+==== KSEG1 under Xinu ====
 === Kernel Segment 2 ===

@@ Line 16: / Line 16: @@
 === User Segment under Xinu ===
-[[Embedded Xinu]] has basic memory management as of the 2.0 release (stored in the <tt>mem/</tt> directory).  During initialization, the kernel allocates some amount of memory (defined in <code>xinu.conf</code> as UHEAP_SIZE) to act as the user memory heap.  Once this memory is initialized, calls to <code>malloc</code> and <code>free</code> will use the user heap for memory allocation and automatically insert mappings into the system page table.  All mappings are 1-1 since there is no backing store for a virtual memory subsystem, though it would be possible to provide each thread with a private address space this requires lots of memory overhead.
+[[Embedded Xinu]] has basic [[memory management]] as of the 2.0 release (stored in the <tt>mem/</tt> directory).  During initialization, the kernel allocates some amount of memory (defined in <code>xinu.conf</code> as UHEAP_SIZE) to act as the user memory heap.  Once this memory is initialized, calls to <code>malloc</code> and <code>free</code> will use the user heap for memory allocation and automatically insert mappings into the system page table.  All mappings are 1-1 since there is no backing store for a virtual memory subsystem, though it would be possible to provide each thread with a private address space this requires lots of memory overhead.
 Exception code to handle TLB faults is in the <code>tlbMissHandler</code> function and simply performs a lookup of the faulting address in the system page table, checks to see if it is valid and in the correct address space, and inserts the mapping in the TLB hardware.

@@ Line 44: / Line 44: @@
 After the reserved system page, the operating system is free to use memory however it sees fit.
-=== KSEG0 under Xinu ===
+==== KSEG0 under Xinu ====
 [[Embedded Xinu]] uses KSEG0 extensively for kernel operations.  As the WRT54GL uses a 32-bit MIPS processor, Embedded Xinu loads a quick TLB handler into memory at <tt>0x8000 0000</tt> and a generic exception handler at <tt>0x8000 0180</tt>, both of these are limited to 32 instructions and jump to higher level C code when needed.  It is important to note that Embedded Xinu also makes use of reserved memory starting at <tt>0x8000 0200</tt> to store an array of exception handler entry points (32-bit function pointers for 32 possible exceptions) and <tt>0x8000 0280</tt> to store an array of interrupt handler entry points (32-bit function pointers for 8 possible interrupts).

@@ Line 32: / Line 32: @@
 === Kernel Segment 0 ===
-This segment exists from memory address <tt>0x8000 0000</tt> to <tt>0x9FFF FFFF</tt> and is cached but remains unmapped (beyond the simple address - <tt>0x8000 0000</tt> mapping).
+The first kernel segment, or KSEG0, is the range of memory addresses from <tt>0x8000 0000</tt> through <tt>0x9FFF FFFF</tt>.  This memory unmapped and cached, meaning that when the processor attempts to access an address in this range it will not consult the memory manager for a mapping, but will store and modifications in the on-chip memory cache.  '''Note''' that when allocating memory for a device driver that will be using DMA, the caching effects could lead to major headaches.  If memory is being given to a hardware backend it should be mapped into the range of [[#Kernel Segment 1|KSEG1]].
-The first 0x1000 bytes of this segment are reserved system space and contains small amounts of code for the [[interrupt handler]].  When an interrupt or exception occurs, the MIPS processor will jump to code located at <tt>0x8000 0180</tt>, expecting to find handler code at that location.  For safety reasons that code can only consume 0x20 bytes of memory (enough to jump to a safer, more robust handler).  [[Embedded XINU]] takes advantage of the space immediately after the end of interrupt handling code by loading entry vectors for the various interrupts and exceptions for speedy lookup.
+On many MIPS processors the first page (4096 bytes) of KSEG0 is considered to be reserved system space where small amounts of specialized code can be loaded for fast execution.  Typically, this memory is used for exception handling and the following sections are reserved for the following:
-After the reserved system space it is safe to load generic code, XINU code is loaded to <tt>0x8000 1000</tt> and begins execution at the same offset.  XINU code begins with the text segment, followed by the data and BSS segments.  After the compiled image is loaded into RAM, XINU allocates a specific amount of memory for the kernel stack immediately after the BSS segment.  Once the kernel stack has been setup, XINU initializes the heap beginning directly above the kernel stack and continuing until the end of physical memory (<tt>0x80FF FFFF</tt>).
+* <tt>0x8000 0000</tt> (32 instructions) is for the TLB exception handler,
-Kernel memory allocation will take memory addresses from the heap initialized in this segment.
+Other reserved portions of this memory page remain unknown.
 === Kernel Segment 1 ===

@@ Line 1: / Line 1: @@
 Memory on MIPS-based processors is broken into several segments, consuming the entire 32-address space.  These segments are arranged as follows:
-* [[#User Segment|User Segment]] (USEG), 2 GB mapped and cached, addresses <tt>0x0000 0000</tt> through <tt>0x7FFF FFFF</tt>
+* [[#User Segment|User Segment]] (USEG), 2 GB '''mapped''' and '''cached''', addresses <tt>0x0000 0000</tt> through <tt>0x7FFF FFFF</tt>
-* [[#Kernel Segment 0|Kernel Segment 0]] (KSEG0), 512 MB unmapped and cached, addresses <tt>0x8000 0000</tt> through <tt>0x9FFF FFFF</tt>
+* [[#Kernel Segment 0|Kernel Segment 0]] (KSEG0), 512 MB '''unmapped''' and '''cached''', addresses <tt>0x8000 0000</tt> through <tt>0x9FFF FFFF</tt>
-* [[#Kernel Segment 1|Kernel Segment 1]] (KSEG1), 512 MB unmapped and uncached, addresses <tt>0xA000 0000</tt> through <tt>0xBFFF FFFF</tt>
+* [[#Kernel Segment 1|Kernel Segment 1]] (KSEG1), 512 MB '''unmapped''' and '''uncached''', addresses <tt>0xA000 0000</tt> through <tt>0xBFFF FFFF</tt>
-* [[#Kernel Segment 2|Kernel Segment 2]] (KSEG2), 1 GB mapped and cached, addresses <tt>0xC000 0000</tt> through <tt>0xFFFF FFFF</tt>
+* [[#Kernel Segment 2|Kernel Segment 2]] (KSEG2), 1 GB '''mapped''' and '''cached''', addresses <tt>0xC000 0000</tt> through <tt>0xFFFF FFFF</tt>
 Note that the [[WRT54GL]] only has 16 MB of main memory, so a 1-1 mapping is not be available above <tt>0x..FF FFFF</tt>.