Difference between revisions of "Exception and Interrupt Handling"

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(Brief description of the interrupt handler)
 
 
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Embedded XINU utilizes a interrupt handling system which allows components to register custom interrupt handlers to the system at runtime or use the default trap handler.
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[[Embedded XINU]] utilizes a interrupt handling system which allows components to register custom interrupt handlers to the system at runtime or fall-back to the default trap handler.
  
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Since interrupt handling code can occupy at most 0x20 bytes of memory in the reserved system area, the interrupt handler must be efficient and robust.  When an exception occurs the handler checks the cause register for the number of the exception, loads the known offset to the interrupt vector table (0x8000 0200) and adds the exception number to that offset.  After the address of the exception handler is known, it is loaded into a register, checks if it is the NULL pointer (not set) and jumps to the handler code.  If the handler is set to NULL, the code uses the default trap handler instead.
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MIPS processors will jump to and execute code beginning at <tt>0x8000 0180</tt> when an exception or interrupt occurs.  Code for handling traps must occupy no more than 0x20 bytes at this location (eight instructions), therefore Embedded XINU uses three instructions to jump to different code which will handle traps more robustly.
  
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Interrupt handling occurs in a similar fashion, but relies on saving the state of the system which cannot occur in the simple interrupt handler.
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In order to handle exceptions (such as TLB misses) efficiently, Embedded XINU uses an interrupt vector system to quickly read the exception code, load the registered exception handler, and jump to the handler.  If any of these steps do not exist, the handler will fall-back to the default trap handler.
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If an interrupt has occurred it is important to save the state of the processor and handle the interrupt gracefully so the system can continue running.  Thus, if the interrupt handler was called by an interrupt and not an exception, the code will save the state of the processor and perform a similar lookup for interrupt handlers.

Latest revision as of 18:51, 27 May 2008

Embedded XINU utilizes a interrupt handling system which allows components to register custom interrupt handlers to the system at runtime or fall-back to the default trap handler.

MIPS processors will jump to and execute code beginning at 0x8000 0180 when an exception or interrupt occurs. Code for handling traps must occupy no more than 0x20 bytes at this location (eight instructions), therefore Embedded XINU uses three instructions to jump to different code which will handle traps more robustly.

In order to handle exceptions (such as TLB misses) efficiently, Embedded XINU uses an interrupt vector system to quickly read the exception code, load the registered exception handler, and jump to the handler. If any of these steps do not exist, the handler will fall-back to the default trap handler.

If an interrupt has occurred it is important to save the state of the processor and handle the interrupt gracefully so the system can continue running. Thus, if the interrupt handler was called by an interrupt and not an exception, the code will save the state of the processor and perform a similar lookup for interrupt handlers.

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