Talk:Memory/Archive1

This is how the page originally appeared, before cleaning up Michael 15:10, 18 September 2007 (CDT)

------------
|0x0000 0000    User Segment
| 0x00FF FFFF   End of 16 MB physical ram
|
|0x7FFF FFFF
------------
|0x8000 0000    Kernel Segment 0 (KSEG0) Unmapped, cached.
|               Translates to lowest 512 MB of physical memory.
|               Ideal for kernel.
|
|+-----------
||0x8000 0180   Interrupt vector
||0x8000 0200
|+-----------
|
|+-----------
||0x8000 1000   Kernel entry point.
||              Kernel text, data, heap, and stack segments
||0x80FF FFFF   End of 16MB physical ram
|+-----------
|
|0x9FFF FFFF
------------
|0xA000 0000    Kernel Segment 1 (KSEG1) Unmapped, uncached.
|               Translates (again) to lowest 512 MB of physical memory.
|               Ideal for memory-mapped I/O ports.
|
|+------------
||0xB800 0000   Broadcom I/O Controller [ IRQ 3 ]
||+-----------
|||0xB800 0060  GPIO
|||0xB800 006F
||+-----------
||+-----------
|||0xB800 0300  UART 0
|||0xB800 0307
||+-----------
||
||+-----------
|||0xB800 0400  UART 1
|||0xB800 0407
||+-----------
||
||
|+------------
||0xB800 1000   Broadcom Ethernet 47xx (4401?) [ IRQ 4 ]
||
|+------------
||0xB800 2000   Mips 32 CPU [ IRQ 5 ]
||
|+------------
||0xB800 3000   Broadcom USB Controller [ IRQ 6 ]
||
|+------------
||0xB800 4000   DD SDRAM Controller [ IRQ 3 ]
||
|+------------
||0xB800 5000   Broadcom Wireless LAN Controller [ IRQ 2 ]
||
|+------------
||0xB800 6000   Broadcom 47xx Robo Switch Core [ IRQ 3 ]
||
|+------------
||0xBC00 0000   Flash RAM (4 MB)
||+-----------
|||0xBC00 0000  flash0.boot (256 KB)
|||
|||0xBC03 FFFF
||+-----------
|||0xBC04 0000  flash0.trx
|||
|||0xBC04 001B or 0xBC04 03FF
||+-----------
|||0xBC04 001C or 0xBC04 0400
|||             flash0.os (3808 KB)
|||0xBC3F 7FFF
||+-----------
|||0xBC3F 8000  flash0.nvram (32 KB)
|||
|||0xBC3F FFFF
||+-----------
||0xBC3F FFFF
|+------------
|0xBFFF FFFF
------------
|0xC000 0000    Kernel Segment 2 (KSEG2)
|0xFFFF FFFF
------------