Memory on the WRT54GL is still (on the whole) not fully understood, this page is dedicated to rectifying that problem. View the talk page for a simple (possibly outdated) dump of what memory should look like.
Memory on almost every MIPS processor is broken into two major sections---user memory and kernel memory. Each of these sections occupies two gigabytes of memory and provides a simple mapping from code addresses to physical addresses which will be explained later.
User memory, also known as KUSEG, ranges from 0x0000 0000 to 0x7FFF FFFF and can only be accessed when the processor is running in user-mode or (more dangerously) if the error level bit in the status register of co-processor 0 is set. While executing in kernel-mode or supervisor-mode memory references to this segment will result in TLB exceptions.
Since the WRT54GL routers only have 16 megabytes of RAM, it is currently assumed that 0x0000 0000--0x00FF FFFF has a 1-1 mapping with physical memory.
Kernel memory occupies the processor memory range from 0x8000 0000 to 0xFFFF FFFF and is sub-divided into 3 smaller regions. These regions are:
- KSEG0 -- unmapped, cached memory (512 megabytes, starting at 0x8000 0000),
- KSEG1 -- unmapped, uncached memory (512 megabytes, starting at 0xA000 0000),
- KSEG2 -- mapped memory (1 gigabytes, starting at 0xC000 0000).
It is important to notice that all direct memory accesses (DMAs) occur in the unmapped, uncached region of memory since devices often produce volatile data which would be dangerous to cache.
Since physical memory is shared between user and kernel processes the mapping for KUSEG is simply 1-1, KSEG0 is address - 0x8000 0000, KSEG1 is address - 0xA000 0000, and finally KSEG2 is address - 0xC000 0000.