Difference between revisions of "UART Driver"

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The UART driver is a char-oriented driver designed to work with a [[National Semiconductor 16550 UART]].  The driver is responsible for receiving and sending bytes of data asynchronously.  The UART driver still needs work in the area of utilizing the FIFO capabiities of the 16550 UART.
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[[Image:UartAsyncDriver.png|right|450px]]
== Conceptual structure ==
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The UART driver is a char-oriented driver designed to work with a [[National Semiconductor 16550 UART]].  The driver is responsible for receiving and sending bytes of data asynchronously.   
The UART driver is divided into two sections: an upper half and a lower half.  The two halves communicate via semaphores and buffers.
 
  
[[Image:UartAsyncDriver.png]]
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The UART driver is divided into two sections: an upper half and a lower half.  The two halves communicate via semaphores and buffers.  The lower half is interrupt driven and interacts with the physical hardware.  The upper half of the driver interacts with user programs.  It does not interact directly with the hardware nor does it spinlock while waiting for the hardware to be ready.  The upper half waits on semaphores which are signaled by the lower half to indicate bytes of data or free space are avaialable in the appropriate buffer.  
  
The lower half is interrupt driven and interacts with the physical hardwareThe 16550 UART sends an interrupt (if enabled) when the transmitter is empty or the receiver has a byte. The lower half of the driver handles these interrupts. When data is received, the lower half places the received byte into the input buffer and signals on the input semaphore to make the upper half aware another byte is in the input buffer. When a transmitter empty interrupt occurs, the lower half moves bytes from the output buffer into the transmitter and signals the output semaphore to make the upper half aware another free byte is in the output buffer.
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== Physical UART ==
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The XINU backends have been equipped with serial ports that are representative of the National Semiconductor 16550 UARTDocumentation on the 16550 UART can be found at [http://www.national.com/ds.cgi/NS/NS16C552.pdf http://www.national.com/ds.cgi/NS/NS16C552.pdf].
  
The upper half of the driver interacts with user programs.  It does not interact directly with the hardware nor does it spinlock while waiting for the hardware to be ready.  The upper half waits on semaphores which are signaled by the lower half to indicate bytes of data or free space are avaialable in the appropriate buffer.  Read removes data from the input buffer and places it in a user supplied buffer and returns.  Write places data into the output buffer from a user supplied buffer and returns.
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== Initialization ==
 
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Intialize defines the starting values for all members of the control block: statistical counts are zeroed, buffers are defined, and semaphores are allocated.  Also part of the initialization process is setting values in the control and status registers:
== Hardware ==
 
The following structure represents the hardware control and status registers:
 
 
 
  /* Control and status registers for the 16550 UART. */
 
  struct uart_csreg
 
  {
 
    volatile unsigned char uart_buffer;  /* receive buffer (read only) & */
 
                                          /*  transmit hold (write only)  */
 
    volatile unsigned char uart_ier;      /* interrupt enable            */
 
    volatile unsigned char uart_iir;      /* interrupt ident (read only)  */
 
                                          /*  or FIFO control (write only)*/
 
    volatile unsigned char uart_lcr;      /* line control                */
 
    volatile unsigned char uart_mcr;      /* modem control                */
 
    volatile unsigned char uart_lsr;      /* line status                  */
 
    volatile unsigned char uart_msr;      /* modem status                */
 
  volatile unsigned char uart_scr;      /* scratch                      */
 
  };
 
 
 
Some registers are also defined with additional or alternative names for coherent reference.
 
 
 
  /* Alternative names for control and status registers */
 
  #define uart_rbr uart_buffer            /* receive buffer (read only)  */
 
  #define uart_thr uart_buffer            /* transmit hold (write only)  */
 
  #define uart_fcr uart_iir              /* FIFO control (write only)    */
 
  #define uart_dll uart_buffer            /* divisor latch low byte      */
 
  #define uart_dlm uart_ier              /* divisor latch high byte      */
 
 
 
See [[National Semiconductor 16550 UART]] for more details about the hardware.
 
 
 
== Control block ==
 
The UART driver uses a structure to track all buffers, semaphores, and counts associated with the UART.
 
 
 
  /* UART 16550 control block */
 
  struct uart
 
  {
 
    /* Pointers to associated structures */
 
    struct uart_csreg *uart_csr;          /* control and status registers */
 
    struct dentry    *uart_dev;          /* dev structure                */
 
    /* Statistical Counts */
 
    int              uart_cout;          /* characters output            */
 
    int              uart_cin;          /* characters input            */
 
    int              uart_lserr;        /* receiver error count        */
 
    int              uart_ovrrn;        /* characters overrun          */
 
    int              uart_iirq;          /* input IRQ count              */
 
    int              uart_oirq;          /* output IRQ count            */
 
    /* UART input fields */
 
    unsigned char    uart_iflags; /* Input flags         */
 
    SEMAPHORE        uart_isema;         /* I/0 semaphore for uart input */
 
    unsigned short    uart_istart; /* Index of first byte          */
 
    unsigned short    uart_icount;        /* Bytes in buffer              */
 
    unsigned char    uart_in[UART_IBLEN];  /* Input buffer              */
 
    /* UART output fields */
 
    unsigned char    uart_oflags; /* Output flags         */
 
    SEMAPHORE        uart_osema;         /* I/0 semaphore for uart output*/
 
    unsigned short    uart_ostart;        /* Index of first byte          */
 
    unsigned short    uart_ocount;        /* Bytes in buffer              */
 
    unsigned char    uart_out[UART_OBLEN]; /* Output buffer              */
 
    int              uart_oidle;        /* UART transmitter idle        */
 
  };
 
 
 
== Functionality ==
 
=== Initialize ===
 
  /* Initialize structure */
 
  DEVCALL uartInit(struct dentry *pdev)
 
 
 
Intialize defines the starting values for all members of the control block: statistical counts are zeroed, buffers are defined, and semaphores are allocated.  Also part of the intialization process is setting values in the control and status registers:
 
* A baud divisor of 0x000B (11d) is set; assuming x16 clock factor, that gives a base crystal frequency of about 20.275 MHz.
 
 
* Line control is set to 8 bit, no parity, 1 stop.
 
* Line control is set to 8 bit, no parity, 1 stop.
 
* Receiver FIFO full, transmitt buffer empty, and receiver line status interrupts are enabled.
 
* Receiver FIFO full, transmitt buffer empty, and receiver line status interrupts are enabled.
 
* Hardware FIFOs are enabled.
 
* Hardware FIFOs are enabled.
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* Divisor Latch bits (high and low)
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** The divisor can be calculated by using the formula:
 +
:<math>divisor=\frac{baud\_base+\frac{baud\_rate}{2}}{baud\_rate}.</math>
 +
Where <tt>baud_rate</tt> is the speed you wish to connect at (typically 115,200) and
 +
:<math>baud\_base=\frac{clockrate}{16}</math>.
 +
The clockrate should be measured in hertz and may not be equivalent to the clockspeed.  (The [[WRT54GL]], for example, has a hard-coded clockrate of 20,000,000 or 20MHz, while the [[WRT54G]] has a clockrate of about 25MHz.)
  
=== Read (Upper Half) ===
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== Upper Half (Read and Write) ==
  /* Read into user buffer (Upper half) */
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Read is part of the upper half of the driver that fills a user supplied buffer with bytes from the input buffer filled by the lower half of the driver. If the input buffer is empty, read waits for the lower half to signal on the input semaphore and indicate bytes are avaiable in the input buffer.
  DEVCALL uartRead(struct dentry *pdev, unsigned char *buf, int len)
 
  /* Read a single character (calls uartRead; Upper Half) */
 
  DEVCALL uartGetChar(struct dentry *pdev)
 
 
 
=== Write (Upper Half) ===
 
  /* Write from user buffer (Upper Half) */
 
  DEVCALL uartWrite(struct dentry *pdev, unsigned char *buf, int len)
 
  /* Write a signle character (calls uartWrite; Upper Half) */
 
  DEVCALL uartPutChar(struct dentry *pdev, unsigned char ch)
 
  
=== Interrupt Handler (Lower Half) ===
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Write is part of the upper half of the driver and places bytes from a user supplied buffer into the output buffer read by the lower half of the driver.  If there is no free space in the output buffer, write waits for the lower half to signal on the output semaphore and indicate free space is available in the output buffer.
  /* Interrupt handler (Lower Half) */
 
  void uartIntr(void)
 
  
=== Control ===
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== Lower Half (Interrupt Handler) ==
  /* Control */
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The interrupt handler is the lower half of the driver.  The 16550 UART sends an interrupt (if enabled) when the transmitter FIFO is empty or the receiver FIFO has reached its available bytes tigger level.
  DEVCALL uartControl(struct dentry *pdev, int func, unsigned char arg1, unsigned char arg2)
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Three different types of interrupts are handled by the lower half:
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* Line or modem status: The interrupt is merely noted in the UART's statistical counts. 
 +
* Receiver hardware FIFO trigger level: The driver moves bytes from the UART's receive hardware FIFO into the input buffer.  Received bytes are read from the UART until the Data Ready bit in the Line Status Register is no longer set.  The input semaphore is signaled to let the upper half know bytes of data are in the input buffer. 
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* Transmitter hardware FIFO empty: The lower half fills the UART's transmit hardware FIFO from the output buffer.  The interrupt handler fills the transmit hardware FIFO until the FIFO is full or the output buffer is empty.  The output semaphore is signaled to let the upper half know bytes of space are available in the output buffer.
  
  /* uartControl() functions */
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== Control ==
  #define UART_IOC_SETIFLAG CHAR_IOC_SETIFLAG    /* set input flags         */
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The control functions are used to set, clear, and get the input and output flags for the UART driver.  Non-blocking flags indicate the upper half read and write functions should perform as much of the requested read or write length as possible, but should not block to wait for the lower half to fill or empty the input or output buffers.  When the echo input flag is set, the UART outputs every byte as it is received in addition to placing the byte in the input buffer.
  #define UART_IOC_CLRIFLAG CHAR_IOC_CLRIFLAG    /* clear input flags */
 
  #define UART_IOC_GETIFLAG CHAR_IOC_GETIFLAG    /* get input flags         */
 
  #define UART_IOC_SETOFLAG CHAR_IOC_SETOFLAG    /* set output flags         */
 
  #define UART_IOC_CLROFLAG CHAR_IOC_CLROFLAG    /* clear output flags       */
 
  #define UART_IOC_GETOFLAG CHAR_IOC_GETOFLAG    /* get output flags        */
 
  
  /* UART input flags */
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=== Loopback ===
  #define      UART_IFLAG_NOBLOCK CHAR_IFLAG_NOBLOCK  /* do non-blocking input  */
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<code>UART_ENABLE_LOOPBACK</code> and <code>UART_DISABLE_LOOPBACK</code> control functions enable and disable hardware loopback.  Be aware that loopback is precarious and must be used carefully.  It is recommended that you turn off interrupts prior to enabling loopback and after disabling loopback to avoid interleaving output while in loopback mode.
  #define      UART_IFLAG_ECHO          CHAR_IFLAG_ECHO      /* echo input              */
 
  
  /* UART output flags */
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Prior to enabling and disabling hardware loopback, the control function ensures the transmitter is completely empty and has completed all previous transmission.  When in loopback mode the hardware does not throw interrupts, so the control functions call the UART interrupt handler explicitly.
  #define UART_OFLAG_NOBLOCK CHAR_OFLAG_NOBLOCK  /* do non-blocking output  */
 
  
 
== See also ==
 
== See also ==
* [[National Semiconductor 16550 UART]]
 
 
* [[TTY Driver]]
 
* [[TTY Driver]]
* [[Why we add serial ports]]
 

Latest revision as of 23:54, 11 September 2008

UartAsyncDriver.png

The UART driver is a char-oriented driver designed to work with a National Semiconductor 16550 UART. The driver is responsible for receiving and sending bytes of data asynchronously.

The UART driver is divided into two sections: an upper half and a lower half. The two halves communicate via semaphores and buffers. The lower half is interrupt driven and interacts with the physical hardware. The upper half of the driver interacts with user programs. It does not interact directly with the hardware nor does it spinlock while waiting for the hardware to be ready. The upper half waits on semaphores which are signaled by the lower half to indicate bytes of data or free space are avaialable in the appropriate buffer.

Physical UART

The XINU backends have been equipped with serial ports that are representative of the National Semiconductor 16550 UART. Documentation on the 16550 UART can be found at http://www.national.com/ds.cgi/NS/NS16C552.pdf.

Initialization

Intialize defines the starting values for all members of the control block: statistical counts are zeroed, buffers are defined, and semaphores are allocated. Also part of the initialization process is setting values in the control and status registers:

  • Line control is set to 8 bit, no parity, 1 stop.
  • Receiver FIFO full, transmitt buffer empty, and receiver line status interrupts are enabled.
  • Hardware FIFOs are enabled.
  • Divisor Latch bits (high and low)
    • The divisor can be calculated by using the formula:
<math>divisor=\frac{baud\_base+\frac{baud\_rate}{2}}{baud\_rate}.</math>

Where baud_rate is the speed you wish to connect at (typically 115,200) and

<math>baud\_base=\frac{clockrate}{16}</math>.

The clockrate should be measured in hertz and may not be equivalent to the clockspeed. (The WRT54GL, for example, has a hard-coded clockrate of 20,000,000 or 20MHz, while the WRT54G has a clockrate of about 25MHz.)

Upper Half (Read and Write)

Read is part of the upper half of the driver that fills a user supplied buffer with bytes from the input buffer filled by the lower half of the driver. If the input buffer is empty, read waits for the lower half to signal on the input semaphore and indicate bytes are avaiable in the input buffer.

Write is part of the upper half of the driver and places bytes from a user supplied buffer into the output buffer read by the lower half of the driver. If there is no free space in the output buffer, write waits for the lower half to signal on the output semaphore and indicate free space is available in the output buffer.

Lower Half (Interrupt Handler)

The interrupt handler is the lower half of the driver. The 16550 UART sends an interrupt (if enabled) when the transmitter FIFO is empty or the receiver FIFO has reached its available bytes tigger level. Three different types of interrupts are handled by the lower half:

  • Line or modem status: The interrupt is merely noted in the UART's statistical counts.
  • Receiver hardware FIFO trigger level: The driver moves bytes from the UART's receive hardware FIFO into the input buffer. Received bytes are read from the UART until the Data Ready bit in the Line Status Register is no longer set. The input semaphore is signaled to let the upper half know bytes of data are in the input buffer.
  • Transmitter hardware FIFO empty: The lower half fills the UART's transmit hardware FIFO from the output buffer. The interrupt handler fills the transmit hardware FIFO until the FIFO is full or the output buffer is empty. The output semaphore is signaled to let the upper half know bytes of space are available in the output buffer.

Control

The control functions are used to set, clear, and get the input and output flags for the UART driver. Non-blocking flags indicate the upper half read and write functions should perform as much of the requested read or write length as possible, but should not block to wait for the lower half to fill or empty the input or output buffers. When the echo input flag is set, the UART outputs every byte as it is received in addition to placing the byte in the input buffer.

Loopback

UART_ENABLE_LOOPBACK and UART_DISABLE_LOOPBACK control functions enable and disable hardware loopback. Be aware that loopback is precarious and must be used carefully. It is recommended that you turn off interrupts prior to enabling loopback and after disabling loopback to avoid interleaving output while in loopback mode.

Prior to enabling and disabling hardware loopback, the control function ensures the transmitter is completely empty and has completed all previous transmission. When in loopback mode the hardware does not throw interrupts, so the control functions call the UART interrupt handler explicitly.

See also